Akademik Veri Yönetim Sistemi
International Journal of Circuit Theory and Applications, 2026 (SCI-Expanded, Scopus)
In digital system applications, multiplication required in many operations is costly and resource-consuming. Multiplication is one of the complex processes that consume considerable processor time. However, because system performance is highly dependent on processor speed and, therefore, on multiplication operation, it is necessary to perform the multiplication operation fast. A commonly used algorithm for efficient signed multiplication is the Booth multiplication (BM) technique. This technique aims to reduce the number of partial products (PPs) in the multiplication operation. In this study, PPs are reduced using the proposed effective BM encoder, and the resulting PPs are added up using different compressor designs. In the PP generation stage, an original adaptation of Gray coding to the Booth encoding stage is employed to reduce hardware consumption and achieve a faster design. Tests have shown that compressors are quite efficient for the high-speed radix-4 and radix-8 system architectures designed for 16 × 16 and 32 × 32 multiplication. The performance metrics of the designed pipelined architectures are compared, the corresponding results are presented, and the designs are implemented on FPGA hardware. It is observed that promising results are obtained in terms of clock frequency.