Akademik Veri Yönetim Sistemi
Journal of Real-Time Image Processing, cilt.20, sa.2, 2023 (SCI-Expanded)
This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) architecture to be used with high-efficiency video coding (HEVC) intra-prediction method in image compression. Since the amount of calculation required by the transform step in HEVC is high and accordingly the power consumption is high, a novel DCT architecture for HEVC is proposed to reduce this calculation complexity and power consumption. This architecture is based on erroneous calculations in the steps, which can be ignored in the quantizing step. For this purpose, approximate 5:3 compressor circuits with different error rates are designed and used instead of addition/subtraction in DCT architecture. This DCT architecture is designed to support 4 × 4, 8 × 8, 16 × 16 and 32 × 32 transform blocks. The designed architecture is performed on FPGA and experiments are conducted. In these experiments, hardware performance parameters are examined, and it is proved that the use of approximate compressor can provide advantages on power consumption and physical area. The efficiency of the proposed architecture is investigated by performing image compression and video coding tests.