Evaluating the hardware performance of a million-bit multiplier
16th Euromicro Conference on Digital System Design, DSD 2013, Santander, İspanya, 4 - 06 Eylül 2013, ss.955-962, (Tam Metin Bildiri)
- Yayın Türü: Bildiri / Tam Metin Bildiri
- Doi Numarası: 10.1109/dsd.2013.108
- Basıldığı Şehir: Santander
- Basıldığı Ülke: İspanya
- Sayfa Sayıları: ss.955-962
- Anahtar Kelimeler: FFT, Homomorphic encryption, Large multiplier, Number theoretical transform
- İstanbul Ticaret Üniversitesi Adresli: Evet
Özet
In this work we present the first full and complete evaluation of a very large multiplication scheme in custom hardware. We designed a novel architecture to realize a million-bit multiplication architecture based on the Schönhage-Strassen Algorithm and the Number Theoretical Transform (NTT). The construction makes use of an innovative cache architecture along with processing elements customized to match the computation and access patterns of the FFT-based recursive multiplication algorithm. When synthesized using a 90nm TSMC library operating at a frequency of 666 MHz, our architecture is able to compute the product of integers in excess of a million bits in 7.74 milliseconds. Estimates show that the performance of our design matches that of previously reported software implementations on a high-end 3 Ghz Intel Xeon processor, while requiring only a tiny fraction of the area. © 2013 IEEE.